This invention relates generally to data processing systems and more particularly to a method and apparatus for eliminating the bus locking requirement normally associated with transactions used to manipulate system locks.
As it is known in the art, data processing systems generally include several types of processing resources which may be interconnected by one or more communication busses. In addition to the processor resources, data processing systems also generally include some sort of memory which is typically shared amongst the processor resources. As is common in many computer systems these processing resources may act independently to perform different processing tasks. Since each of the processing resources may act independently there may arise a situation where there is contention for the shared memory resources within the system.
One example of a data processing system which includes several processing resources coupled to a common memory over one or more busses are data storage systems such as the Symmetrix family of data storage systems manufactured by EMC Corporation. These storage systems are typically capable of being coupled to several different host computers at any given time and provide storage services to each of those computers independently. In order to support transactions between a plurality of host computers simultaneously the storage system includes several host controllers for managing the communication between the host computer and the storage system. In addition, the Symmetrix storage systems mentioned above include several disk controllers which are each responsible for managing one or more arrays of disk type storage devices.
In addition to the host controllers and disk controllers mentioned above the storage subsystem may also contain a very large global memory which is used to manage the transfer of data from the host computers to the storage devices as well as to manage the transfer of data from the storage devices to the host computer.
During the operation of the data storage system described above, it is often necessary for any one or the host controllers or disk controllers to require access to a particular section of the global memory in order to set a system lock in order to guarantee exclusive access to a particular storage system resource. One method known in the art for doing such a process is to perform a so called read/modify/write operation with a lock.
In order to perform such a command, prior art data processing systems require that the requesting processor gain exclusive access to the bus and to the memory storing the lock records. Once the requesting processor gains control of the bus, the bus is locked to all other users connected to the bus. During the period when the bus is locked, the requesting controller will generally read the data from the lock data structure into it's own internal memory. The processor will then operate to modify the data (i.e. write the data necessary to lock the resource) and then write the data back to lock data structure in the memory.
The reason that the bus is generally locked throughout this entire transaction is to prevent another processor from attempting to perform a similar operation. That is for example, if the original processor was modifying the lock record data structure and the bus was not in the lock state, a second processor might read the lock data structure and think that no other processor held the lock on that resource and also attempt to lock the same resource. By locking the entire bus, other processors are prevented from coming in and accessing that particular lock record. The disadvantage of such a scheme is fairly obvious in that not only can other processors not access the shared lock records, the other processors cannot carry on any other transactions over the locked system bus while the first processor is doing those operations necessary to gain a lock on the system resource.
In a system with a dual bus architecture, it might first appear that the system would be able to continue to perform useful work over the second bus while the first bus was locked in order for the first processor to do the lock transaction. However, as described above, the memory with the desired lock record is locked as well. If one of the processors connected to the second bus attempted to gain access to the same memory which was the subject of the first locked transaction in order to perform any memory transaction, the second processor would proceed as described above for the first processor. The second processor would first gain access to the second bus. It would then attempt to access the memory which has already been locked by the first processor. The second processor will wait for the memory to become unlocked so that it can perform its transaction. At this point, both buses and the memory are locked by the two processors trying to accomplish lock transaction to the same memory. It can be seen then that this scenario leads to a situation when the entire system is prevented from doing any useful work because two processors are seeking to get locks on system resources. This problem is extensible to systems of multiple buses and those that may use cross bar switches to provide connectivity between various elements of a data processing system.
Previous methods attempting to solve the above described bus/system lock problem have generally included maintaining a table within the memory indicating which addresses within the memory are locked at any given. In order to perform lock functions, the table would need to be accessed and read. This solution, however, may still lead to the situation where at least one bus in a multi-bus system is locked while the lock records are updated using an exclusive read modify write (with lock) type command.
It would be advantageous therefore to provide a data processing system in which resources such as a memory are shared amongst a plurality of processing devices where hardware locks could be set and reset without requiring that any of the busses be locked and thereby preventing the system from doing useful work.